An Automatic Test Pattern Generator (ATPG) is a software design tool that simulates the overall functionality of the design or individual circuits within the design of an integrated circuit and generates test vectors for testing the overall functionality of the design. Through the use of these at-speed test vectors, an Automatic Testing Equipment (ATE) may provide a particular degree of fault coverage or fault simulation for the circuitry in the product. Specifically, automatic test pattern generation (ATPG) techniques may provide test patterns for stuck-at faults, transition faults and path delay faults. Conventionally, these test vectors are provided in a computer readable file to the ATE or other testers. The ATE is used in a manufacturing environment to test the die at wafer sort and in packaged tests. During wafer-level testing of a die, test signals are provided through input or input/output (I/O) bond pads on the die, and the test results are monitored on output or I/O bond pads.
Testing of digital systems, such as the core logic of an integrated circuit, is typically performed by loading a test pattern or stimulus into scanable memory elements in the system, launching the test data into the system, operating the system in normal mode for one or more clock cycles of the system clock, capturing the response of the system to the test stimulus, unloading the test response from the system and then comparing the response to the response which should have been obtained if the system was operating according to design.
To improve test coverage of individual circuits, DFT tools have been developed to embed test circuitry into the SoC. For example, Built-In Self-Test (BIST) circuitry may be embedded in the IC design to test individual circuit blocks. BIST circuitry is particularly useful for testing circuit blocks that are not readily accessible through the bond pads of the device under test (DUT). Automated DFT tools that generate BIST circuitry, such as memory BIST for testing memory blocks and logic BIST for testing logic blocks, are well known. External I/Os directly receive the results of tests conducted by BIST circuitry. In the alternative, external I/Os receive these results indirectly through boundary scan circuitry embedded in the design. Additional internal embedded test circuitry such as scan chain circuitry may also be added to the design to increase the internal testability of internal sequential designs.
This separate embedded test circuitry requires input and output ports that are separate from the input and output ports of the programmed functions. During normal operations, the functional circuitry operates. In the alternative, during the testing mode of operations, a separate set of test circuitry using the test inputs and outputs are used. Each core and sub-core embedded on a SoC includes its own test input and output ports and needs to be tested individually, without interference from adjacent cores. Wrapper cell is the circuitry attached to the functional elements of a core to provide paths for test data to flow. The test ports are part of the wrapper cell. It generally includes a flip-flop and a multiplexer, and is able to function in a functional mode and a test mode. In the functional mode, the wrapper cell is transparent and normal functional signals are passed through the multiplexer to the functional core. In the test mode, the wrapper cell changes the input signal causing the test input to be passed through the multiplexer.
Scan testing is implemented by chaining several wrapper cells together in a chip register in order to scan test data in and out of the circuit. There are many different schemes for scan testing, but the predominant method is the monolithic scan path approach where the scan elements, such as the wrapper cell and scan chains are connected in a straight path, serial manner.
Scan-in ports may connect directly to scan-in terminals for each core. This makes it possible to select specific internal scan chains or subsets of internal scan chains, however, this is difficult to implement because the total number of available scan ports at the integrated circuit chip boundary typically are exceeded by the total number of scan paths requiring access to these ports.
As such, the suitability of at-speed test vectors depends upon the design of the scan architecture and clock control mechanism corresponding to the testing mode. A very low cost test platform (VLCT), having reduced speed and accuracy requirements, provides an attractive solution to this problem; yet, it has restrictions on the number of scan test ports that can be supported. Presently, the number is restricted to eight scan chains. Unfortunately, many systems having a large number of scan chains either preclude the use of VLCT or the support for at-speed ATPG pattern application using high speed capture clocks. Some solutions use sophisticated masking integrated with the flip-flops in one or more scan chains.
Moreover, difficulties arise in systems having multiple clock domains when the clock sources differ from the test clock signal used to perform the test, when these domains have different clock rates, and/or when signals cross the boundary between these clock domains have different clock frequencies. More particularly, it is not uncommon for a SoC integrated circuit (IC) to include several digital modules having a variety of clocking domains and clock frequencies. Since the elements in one domain operate at a different frequency from that of other domains in the system, special provisions must be made during testing to ensure that signals traversing clock domains are synchronized. Otherwise, the test response from the system will not be repeatable and test results will be unreliable.
Methods have been developed for testing systems in which the ratio of the frequencies of two clock domains is an integer. However, it is not uncommon for digital systems to employ asynchronous clocks whose frequencies are not multiples of each other. Solutions have yet to be developed for clock domains having non-integer frequency ratios. Testing of such systems using normal operating frequency of a digital system is difficult because the phase relationships between the system clocks are not known and are variable over time. In order to achieve very high reliability circuits, it is essential that the logic in all clock domains be tested at full-speed.
Most of these circuits have been tested using test clock rates that are essentially the same as the functional clock rates and disabling all signal paths crossing clock domain boundaries, where the tests are repeated for each clock domain. The primary drawbacks of this approach are that part of the logic is not tested and a series of tests must be performed in order to test all parts of the system. However, even then, it is not possible to obtain results for all parts of the system operating concurrently at speed.
Accordingly, there is a need for a testing method and circuitry which enables testing at the design or functional speed of digital systems having two or more clock domains where the clock domains are asynchronous clocks whose frequencies are not multiples of one another. Specifically, there is a need for a SoC design that uses the VLCT platform, having at-speed transition fault ATPG, where the constraint on the number of scan test ports is expanded beyond eight scan test ports. Testing of the SoC must be conducted across all clock domains and clock frequencies. In addition, the design implementing the use of the VLCT platform must be scaleable.
The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems set forth above.